The Joint Test Action Group developed a 5 pin test access port standard which is commonly referred to as JTAG. JTAG is used for a variety of Integrated Circuit (IC) and board level tests. Currently some commercial tools allow automatic insertion of logic to switch between the IC's main clock and having the JTAG (TCK) clock driven onto the main clock distribution network. This functionality allows the standard JTAG interface to more effectively drive the inputs during test since the non-clock inputs can be scanned in and held steady while a clock is provided to the chip without having to perform another entire boundary scan just to change one signal.
A clock gater is a circuit that combines a latch (with inverted clock) and an AND gate. It has a “gate” input and a “clock” input. The latch with inverted clock ensures the gate (or control) signal cannot change while the clock is high. The gater's output is taken from the AND gate's output. The AND gate gets a slightly delayed clock on one input and the latch's output on its other input. Just before the clock goes high at the AND gate input the latch captures and holds the value of the gate signal. The AND gate will follow the clock with a slight delay if the gate signal was high just before the clock went high at the AND gate. The AND gate will stay low if the gate signal is low just prior to the clock going high. Had just an AND gate been used without the latch the gate signal may have cut short one of the clocks positive pulses, a clock gater prevents this. Typically clock gaters are used to save power by not clocking circuitry when it doesn't need to be active, and also to control functionality such as only clocking a register when you wish to load it with new data.
Prior art has simply multiplexed between the two clocks without ensuring only whole positive clock pulses were presented to the system and without ensuring there was adequate time between the last pulse of the clock being turned off and the first pulse of the clock being turned on. Alternatively custom circuitry (such as pass gates) in the prior art was not provided as standard cells for use in standard cell based designs and that custom circuitry does not work well with standard cell design flows.
Of particular concern is that the prior art does not insert special clock gaters and does not properly time the control of the two (or more) clocks. As a result, it is possible to get a partial clock pulse out of JTAG control circuitry in either the positive (short time at “1”) or negative (short time at “0”) sense. A partial clock can cause erratic behavior from the integrated circuit.